1. Field
The present invention relates to flash memory technology.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping structure in place of the floating gate. Charge trapping memory cells use dielectric material for charge storage that does not cause cell-to-cell interference like that encountered with floating gate technology.
The typical charge trapping flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the dielectric charge storage layer, and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S).
Flash memory devices generally are implemented using NAND or NOR architectures, although others are known, including AND architectures. The NAND architecture is popular for its high density and high speed when applied to data storage applications. The NOR architecture is better suited to other applications, such as code storage, where random byte access is important. In a NAND architecture, the memory cells are arranged in NAND strings that comprise a series of memory cells having switch transistors used to connect the strings to, for example, bit lines and common source lines. The switch transistors are commonly called string select transistors and ground select transistors, and can consist of an FET transistor in series with the string of memory cells, having its gate in a corresponding string select line SSL or ground select line GSL arranged in parallel with the word lines for the memory array. Switch transistors can be used in other types of architectures as well, and used for selecting blocks of memory cells.
In high density charge trapping memory cells including three-dimensional arrays, switch transistors have been implemented using FETs having the same structure as the memory cells, albeit sometimes having wider channels or other modifications. Thus, these switch transistors have charge trapping structures in the gate dielectric. During manufacturing of a charge trapping memory device of this type, charge can accumulate in the gate dielectric of the switch transistors resulting in a wide distribution of switch transistor threshold across the device. This can impact device performance in a number of undesirable ways.
Accordingly, it is desirable to provide a new memory technology suitable for implementation of switch transistors in charge trapping memory devices, including devices arranged in a NAND architecture.